ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 1


   1              		.cpu cortex-m3
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1
   4              		.eabi_attribute 23, 3
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 1
   9              		.eabi_attribute 34, 1
  10              		.eabi_attribute 18, 4
  11              		.file	"system_stm32f1xx.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.section	.text.SystemInit,"ax",%progbits
  16              		.align	1
  17              		.global	SystemInit
  18              		.syntax unified
  19              		.thumb
  20              		.thumb_func
  21              		.fpu softvfp
  23              	SystemInit:
  24              	.LFB65:
  25              		.file 1 "Src/system_stm32f1xx.c"
   1:Src/system_stm32f1xx.c **** /**
   2:Src/system_stm32f1xx.c ****   ******************************************************************************
   3:Src/system_stm32f1xx.c ****   * @file    system_stm32f1xx.c
   4:Src/system_stm32f1xx.c ****   * @author  MCD Application Team
   5:Src/system_stm32f1xx.c ****   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   6:Src/system_stm32f1xx.c ****   * 
   7:Src/system_stm32f1xx.c ****   * 1.  This file provides two functions and one global variable to be called from 
   8:Src/system_stm32f1xx.c ****   *     user application:
   9:Src/system_stm32f1xx.c ****   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  10:Src/system_stm32f1xx.c ****   *                      factors, AHB/APBx prescalers and Flash settings). 
  11:Src/system_stm32f1xx.c ****   *                      This function is called at startup just after reset and 
  12:Src/system_stm32f1xx.c ****   *                      before branch to main program. This call is made inside
  13:Src/system_stm32f1xx.c ****   *                      the "startup_stm32f1xx_xx.s" file.
  14:Src/system_stm32f1xx.c ****   *
  15:Src/system_stm32f1xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16:Src/system_stm32f1xx.c ****   *                                  by the user application to setup the SysTick 
  17:Src/system_stm32f1xx.c ****   *                                  timer or configure other parameters.
  18:Src/system_stm32f1xx.c ****   *                                     
  19:Src/system_stm32f1xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20:Src/system_stm32f1xx.c ****   *                                 be called whenever the core clock is changed
  21:Src/system_stm32f1xx.c ****   *                                 during program execution.
  22:Src/system_stm32f1xx.c ****   *
  23:Src/system_stm32f1xx.c ****   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24:Src/system_stm32f1xx.c ****   *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
  25:Src/system_stm32f1xx.c ****   *    configure the system clock before to branch to main program.
  26:Src/system_stm32f1xx.c ****   *
  27:Src/system_stm32f1xx.c ****   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
  28:Src/system_stm32f1xx.c ****   *    the product used), refer to "HSE_VALUE". 
  29:Src/system_stm32f1xx.c ****   *    When HSE is used as system clock source, directly or through PLL, and you
  30:Src/system_stm32f1xx.c ****   *    are using different crystal you have to adapt the HSE value to your own
  31:Src/system_stm32f1xx.c ****   *    configuration.
  32:Src/system_stm32f1xx.c ****   *        
  33:Src/system_stm32f1xx.c ****   ******************************************************************************
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 2


  34:Src/system_stm32f1xx.c ****   * @attention
  35:Src/system_stm32f1xx.c ****   *
  36:Src/system_stm32f1xx.c ****   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  37:Src/system_stm32f1xx.c ****   * All rights reserved.</center></h2>
  38:Src/system_stm32f1xx.c ****   *
  39:Src/system_stm32f1xx.c ****   * This software component is licensed by ST under BSD 3-Clause license,
  40:Src/system_stm32f1xx.c ****   * the "License"; You may not use this file except in compliance with the
  41:Src/system_stm32f1xx.c ****   * License. You may obtain a copy of the License at:
  42:Src/system_stm32f1xx.c ****   *                        opensource.org/licenses/BSD-3-Clause
  43:Src/system_stm32f1xx.c ****   *
  44:Src/system_stm32f1xx.c ****   ******************************************************************************
  45:Src/system_stm32f1xx.c ****   */
  46:Src/system_stm32f1xx.c **** 
  47:Src/system_stm32f1xx.c **** /** @addtogroup CMSIS
  48:Src/system_stm32f1xx.c ****   * @{
  49:Src/system_stm32f1xx.c ****   */
  50:Src/system_stm32f1xx.c **** 
  51:Src/system_stm32f1xx.c **** /** @addtogroup stm32f1xx_system
  52:Src/system_stm32f1xx.c ****   * @{
  53:Src/system_stm32f1xx.c ****   */  
  54:Src/system_stm32f1xx.c ****   
  55:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Includes
  56:Src/system_stm32f1xx.c ****   * @{
  57:Src/system_stm32f1xx.c ****   */
  58:Src/system_stm32f1xx.c **** 
  59:Src/system_stm32f1xx.c **** #include "stm32f1xx.h"
  60:Src/system_stm32f1xx.c **** 
  61:Src/system_stm32f1xx.c **** /**
  62:Src/system_stm32f1xx.c ****   * @}
  63:Src/system_stm32f1xx.c ****   */
  64:Src/system_stm32f1xx.c **** 
  65:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
  66:Src/system_stm32f1xx.c ****   * @{
  67:Src/system_stm32f1xx.c ****   */
  68:Src/system_stm32f1xx.c **** 
  69:Src/system_stm32f1xx.c **** /**
  70:Src/system_stm32f1xx.c ****   * @}
  71:Src/system_stm32f1xx.c ****   */
  72:Src/system_stm32f1xx.c **** 
  73:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Defines
  74:Src/system_stm32f1xx.c ****   * @{
  75:Src/system_stm32f1xx.c ****   */
  76:Src/system_stm32f1xx.c **** 
  77:Src/system_stm32f1xx.c **** #if !defined  (HSE_VALUE) 
  78:Src/system_stm32f1xx.c ****   #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
  79:Src/system_stm32f1xx.c ****                                                 This value can be provided and adapted by the user 
  80:Src/system_stm32f1xx.c **** #endif /* HSE_VALUE */
  81:Src/system_stm32f1xx.c **** 
  82:Src/system_stm32f1xx.c **** #if !defined  (HSI_VALUE)
  83:Src/system_stm32f1xx.c ****   #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
  84:Src/system_stm32f1xx.c ****                                                 This value can be provided and adapted by the user 
  85:Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
  86:Src/system_stm32f1xx.c **** 
  87:Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM  */ 
  88:Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
  89:Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
  90:Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 3


  91:Src/system_stm32f1xx.c **** 
  92:Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
  93:Src/system_stm32f1xx.c ****      Internal SRAM. */ 
  94:Src/system_stm32f1xx.c **** /* #define VECT_TAB_SRAM */
  95:Src/system_stm32f1xx.c **** #define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
  96:Src/system_stm32f1xx.c ****                                   This value must be a multiple of 0x200. */
  97:Src/system_stm32f1xx.c **** 
  98:Src/system_stm32f1xx.c **** 
  99:Src/system_stm32f1xx.c **** /**
 100:Src/system_stm32f1xx.c ****   * @}
 101:Src/system_stm32f1xx.c ****   */
 102:Src/system_stm32f1xx.c **** 
 103:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Macros
 104:Src/system_stm32f1xx.c ****   * @{
 105:Src/system_stm32f1xx.c ****   */
 106:Src/system_stm32f1xx.c **** 
 107:Src/system_stm32f1xx.c **** /**
 108:Src/system_stm32f1xx.c ****   * @}
 109:Src/system_stm32f1xx.c ****   */
 110:Src/system_stm32f1xx.c **** 
 111:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Variables
 112:Src/system_stm32f1xx.c ****   * @{
 113:Src/system_stm32f1xx.c ****   */
 114:Src/system_stm32f1xx.c **** 
 115:Src/system_stm32f1xx.c ****   /* This variable is updated in three ways:
 116:Src/system_stm32f1xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 117:Src/system_stm32f1xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 118:Src/system_stm32f1xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
 119:Src/system_stm32f1xx.c ****          Note: If you use this function to configure the system clock; then there
 120:Src/system_stm32f1xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
 121:Src/system_stm32f1xx.c ****                variable is updated automatically.
 122:Src/system_stm32f1xx.c ****   */
 123:Src/system_stm32f1xx.c **** uint32_t SystemCoreClock = 16000000;
 124:Src/system_stm32f1xx.c **** const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 125:Src/system_stm32f1xx.c **** const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
 126:Src/system_stm32f1xx.c **** 
 127:Src/system_stm32f1xx.c **** /**
 128:Src/system_stm32f1xx.c ****   * @}
 129:Src/system_stm32f1xx.c ****   */
 130:Src/system_stm32f1xx.c **** 
 131:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
 132:Src/system_stm32f1xx.c ****   * @{
 133:Src/system_stm32f1xx.c ****   */
 134:Src/system_stm32f1xx.c **** 
 135:Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
 136:Src/system_stm32f1xx.c **** #ifdef DATA_IN_ExtSRAM
 137:Src/system_stm32f1xx.c ****   static void SystemInit_ExtMemCtl(void); 
 138:Src/system_stm32f1xx.c **** #endif /* DATA_IN_ExtSRAM */
 139:Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 140:Src/system_stm32f1xx.c **** 
 141:Src/system_stm32f1xx.c **** /**
 142:Src/system_stm32f1xx.c ****   * @}
 143:Src/system_stm32f1xx.c ****   */
 144:Src/system_stm32f1xx.c **** 
 145:Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
 146:Src/system_stm32f1xx.c ****   * @{
 147:Src/system_stm32f1xx.c ****   */
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 4


 148:Src/system_stm32f1xx.c **** 
 149:Src/system_stm32f1xx.c **** /**
 150:Src/system_stm32f1xx.c ****   * @brief  Setup the microcontroller system
 151:Src/system_stm32f1xx.c ****   *         Initialize the Embedded Flash Interface, the PLL and update the 
 152:Src/system_stm32f1xx.c ****   *         SystemCoreClock variable.
 153:Src/system_stm32f1xx.c ****   * @note   This function should be used only after reset.
 154:Src/system_stm32f1xx.c ****   * @param  None
 155:Src/system_stm32f1xx.c ****   * @retval None
 156:Src/system_stm32f1xx.c ****   */
 157:Src/system_stm32f1xx.c **** void SystemInit (void)
 158:Src/system_stm32f1xx.c **** {
  26              		.loc 1 158 0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 0
  29              		@ frame_needed = 0, uses_anonymous_args = 0
  30              		@ link register save eliminated.
 159:Src/system_stm32f1xx.c ****   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
 160:Src/system_stm32f1xx.c ****   /* Set HSION bit */
 161:Src/system_stm32f1xx.c ****   RCC->CR |= 0x00000001U;
  31              		.loc 1 161 0
  32 0000 0F4B     		ldr	r3, .L2
  33 0002 1A68     		ldr	r2, [r3]
  34 0004 42F00102 		orr	r2, r2, #1
  35 0008 1A60     		str	r2, [r3]
 162:Src/system_stm32f1xx.c **** 
 163:Src/system_stm32f1xx.c ****   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
 164:Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)
 165:Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xF8FF0000U;
  36              		.loc 1 165 0
  37 000a 5968     		ldr	r1, [r3, #4]
  38 000c 0D4A     		ldr	r2, .L2+4
  39 000e 0A40     		ands	r2, r2, r1
  40 0010 5A60     		str	r2, [r3, #4]
 166:Src/system_stm32f1xx.c **** #else
 167:Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xF0FF0000U;
 168:Src/system_stm32f1xx.c **** #endif /* STM32F105xC */   
 169:Src/system_stm32f1xx.c ****   
 170:Src/system_stm32f1xx.c ****   /* Reset HSEON, CSSON and PLLON bits */
 171:Src/system_stm32f1xx.c ****   RCC->CR &= 0xFEF6FFFFU;
  41              		.loc 1 171 0
  42 0012 1A68     		ldr	r2, [r3]
  43 0014 22F08472 		bic	r2, r2, #17301504
  44 0018 22F48032 		bic	r2, r2, #65536
  45 001c 1A60     		str	r2, [r3]
 172:Src/system_stm32f1xx.c **** 
 173:Src/system_stm32f1xx.c ****   /* Reset HSEBYP bit */
 174:Src/system_stm32f1xx.c ****   RCC->CR &= 0xFFFBFFFFU;
  46              		.loc 1 174 0
  47 001e 1A68     		ldr	r2, [r3]
  48 0020 22F48022 		bic	r2, r2, #262144
  49 0024 1A60     		str	r2, [r3]
 175:Src/system_stm32f1xx.c **** 
 176:Src/system_stm32f1xx.c ****   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
 177:Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xFF80FFFFU;
  50              		.loc 1 177 0
  51 0026 5A68     		ldr	r2, [r3, #4]
  52 0028 22F4FE02 		bic	r2, r2, #8323072
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 5


  53 002c 5A60     		str	r2, [r3, #4]
 178:Src/system_stm32f1xx.c **** 
 179:Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
 180:Src/system_stm32f1xx.c ****   /* Reset PLL2ON and PLL3ON bits */
 181:Src/system_stm32f1xx.c ****   RCC->CR &= 0xEBFFFFFFU;
 182:Src/system_stm32f1xx.c **** 
 183:Src/system_stm32f1xx.c ****   /* Disable all interrupts and clear pending bits  */
 184:Src/system_stm32f1xx.c ****   RCC->CIR = 0x00FF0000U;
 185:Src/system_stm32f1xx.c **** 
 186:Src/system_stm32f1xx.c ****   /* Reset CFGR2 register */
 187:Src/system_stm32f1xx.c ****   RCC->CFGR2 = 0x00000000U;
 188:Src/system_stm32f1xx.c **** #elif defined(STM32F100xB) || defined(STM32F100xE)
 189:Src/system_stm32f1xx.c ****   /* Disable all interrupts and clear pending bits  */
 190:Src/system_stm32f1xx.c ****   RCC->CIR = 0x009F0000U;
 191:Src/system_stm32f1xx.c **** 
 192:Src/system_stm32f1xx.c ****   /* Reset CFGR2 register */
 193:Src/system_stm32f1xx.c ****   RCC->CFGR2 = 0x00000000U;      
 194:Src/system_stm32f1xx.c **** #else
 195:Src/system_stm32f1xx.c ****   /* Disable all interrupts and clear pending bits  */
 196:Src/system_stm32f1xx.c ****   RCC->CIR = 0x009F0000U;
  54              		.loc 1 196 0
  55 002e 4FF41F02 		mov	r2, #10420224
  56 0032 9A60     		str	r2, [r3, #8]
 197:Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
 198:Src/system_stm32f1xx.c ****     
 199:Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
 200:Src/system_stm32f1xx.c ****   #ifdef DATA_IN_ExtSRAM
 201:Src/system_stm32f1xx.c ****     SystemInit_ExtMemCtl(); 
 202:Src/system_stm32f1xx.c ****   #endif /* DATA_IN_ExtSRAM */
 203:Src/system_stm32f1xx.c **** #endif 
 204:Src/system_stm32f1xx.c **** 
 205:Src/system_stm32f1xx.c **** #ifdef VECT_TAB_SRAM
 206:Src/system_stm32f1xx.c ****   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 207:Src/system_stm32f1xx.c **** #else
 208:Src/system_stm32f1xx.c ****   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
  57              		.loc 1 208 0
  58 0034 044B     		ldr	r3, .L2+8
  59 0036 4FF00062 		mov	r2, #134217728
  60 003a 9A60     		str	r2, [r3, #8]
 209:Src/system_stm32f1xx.c **** #endif 
 210:Src/system_stm32f1xx.c **** }
  61              		.loc 1 210 0
  62 003c 7047     		bx	lr
  63              	.L3:
  64 003e 00BF     		.align	2
  65              	.L2:
  66 0040 00100240 		.word	1073876992
  67 0044 0000FFF8 		.word	-117506048
  68 0048 00ED00E0 		.word	-536810240
  69              		.cfi_endproc
  70              	.LFE65:
  72              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  73              		.align	1
  74              		.global	SystemCoreClockUpdate
  75              		.syntax unified
  76              		.thumb
  77              		.thumb_func
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 6


  78              		.fpu softvfp
  80              	SystemCoreClockUpdate:
  81              	.LFB66:
 211:Src/system_stm32f1xx.c **** 
 212:Src/system_stm32f1xx.c **** /**
 213:Src/system_stm32f1xx.c ****   * @brief  Update SystemCoreClock variable according to Clock Register Values.
 214:Src/system_stm32f1xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 215:Src/system_stm32f1xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 216:Src/system_stm32f1xx.c ****   *         other parameters.
 217:Src/system_stm32f1xx.c ****   *           
 218:Src/system_stm32f1xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 219:Src/system_stm32f1xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 220:Src/system_stm32f1xx.c ****   *         based on this variable will be incorrect.         
 221:Src/system_stm32f1xx.c ****   *     
 222:Src/system_stm32f1xx.c ****   * @note   - The system frequency computed by this function is not the real 
 223:Src/system_stm32f1xx.c ****   *           frequency in the chip. It is calculated based on the predefined 
 224:Src/system_stm32f1xx.c ****   *           constant and the selected clock source:
 225:Src/system_stm32f1xx.c ****   *             
 226:Src/system_stm32f1xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 227:Src/system_stm32f1xx.c ****   *                                              
 228:Src/system_stm32f1xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 229:Src/system_stm32f1xx.c ****   *                          
 230:Src/system_stm32f1xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
 231:Src/system_stm32f1xx.c ****   *             or HSI_VALUE(*) multiplied by the PLL factors.
 232:Src/system_stm32f1xx.c ****   *         
 233:Src/system_stm32f1xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
 234:Src/system_stm32f1xx.c ****   *             8 MHz) but the real value may vary depending on the variations
 235:Src/system_stm32f1xx.c ****   *             in voltage and temperature.   
 236:Src/system_stm32f1xx.c ****   *    
 237:Src/system_stm32f1xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
 238:Src/system_stm32f1xx.c ****   *              8 MHz or 25 MHz, depending on the product used), user has to ensure
 239:Src/system_stm32f1xx.c ****   *              that HSE_VALUE is same as the real frequency of the crystal used.
 240:Src/system_stm32f1xx.c ****   *              Otherwise, this function may have wrong result.
 241:Src/system_stm32f1xx.c ****   *                
 242:Src/system_stm32f1xx.c ****   *         - The result of this function could be not correct when using fractional
 243:Src/system_stm32f1xx.c ****   *           value for HSE crystal.
 244:Src/system_stm32f1xx.c ****   * @param  None
 245:Src/system_stm32f1xx.c ****   * @retval None
 246:Src/system_stm32f1xx.c ****   */
 247:Src/system_stm32f1xx.c **** void SystemCoreClockUpdate (void)
 248:Src/system_stm32f1xx.c **** {
  82              		.loc 1 248 0
  83              		.cfi_startproc
  84              		@ args = 0, pretend = 0, frame = 0
  85              		@ frame_needed = 0, uses_anonymous_args = 0
  86              		@ link register save eliminated.
  87              	.LVL0:
 249:Src/system_stm32f1xx.c ****   uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
 250:Src/system_stm32f1xx.c **** 
 251:Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
 252:Src/system_stm32f1xx.c ****   uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
 253:Src/system_stm32f1xx.c **** #endif /* STM32F105xC */
 254:Src/system_stm32f1xx.c **** 
 255:Src/system_stm32f1xx.c **** #if defined(STM32F100xB) || defined(STM32F100xE)
 256:Src/system_stm32f1xx.c ****   uint32_t prediv1factor = 0U;
 257:Src/system_stm32f1xx.c **** #endif /* STM32F100xB or STM32F100xE */
 258:Src/system_stm32f1xx.c ****     
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 7


 259:Src/system_stm32f1xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 260:Src/system_stm32f1xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
  88              		.loc 1 260 0
  89 0000 1F4B     		ldr	r3, .L15
  90 0002 5B68     		ldr	r3, [r3, #4]
  91 0004 03F00C03 		and	r3, r3, #12
  92              	.LVL1:
 261:Src/system_stm32f1xx.c ****   
 262:Src/system_stm32f1xx.c ****   switch (tmp)
  93              		.loc 1 262 0
  94 0008 042B     		cmp	r3, #4
  95 000a 14D0     		beq	.L6
  96 000c 082B     		cmp	r3, #8
  97 000e 16D0     		beq	.L7
  98 0010 1BB1     		cbz	r3, .L13
 263:Src/system_stm32f1xx.c ****   {
 264:Src/system_stm32f1xx.c ****     case 0x00U:  /* HSI used as system clock */
 265:Src/system_stm32f1xx.c ****       SystemCoreClock = HSI_VALUE;
 266:Src/system_stm32f1xx.c ****       break;
 267:Src/system_stm32f1xx.c ****     case 0x04U:  /* HSE used as system clock */
 268:Src/system_stm32f1xx.c ****       SystemCoreClock = HSE_VALUE;
 269:Src/system_stm32f1xx.c ****       break;
 270:Src/system_stm32f1xx.c ****     case 0x08U:  /* PLL used as system clock */
 271:Src/system_stm32f1xx.c **** 
 272:Src/system_stm32f1xx.c ****       /* Get PLL clock source and multiplication factor ----------------------*/
 273:Src/system_stm32f1xx.c ****       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 274:Src/system_stm32f1xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 275:Src/system_stm32f1xx.c ****       
 276:Src/system_stm32f1xx.c **** #if !defined(STM32F105xC) && !defined(STM32F107xC)      
 277:Src/system_stm32f1xx.c ****       pllmull = ( pllmull >> 18U) + 2U;
 278:Src/system_stm32f1xx.c ****       
 279:Src/system_stm32f1xx.c ****       if (pllsource == 0x00U)
 280:Src/system_stm32f1xx.c ****       {
 281:Src/system_stm32f1xx.c ****         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 282:Src/system_stm32f1xx.c ****         SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
 283:Src/system_stm32f1xx.c ****       }
 284:Src/system_stm32f1xx.c ****       else
 285:Src/system_stm32f1xx.c ****       {
 286:Src/system_stm32f1xx.c ****  #if defined(STM32F100xB) || defined(STM32F100xE)
 287:Src/system_stm32f1xx.c ****        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
 288:Src/system_stm32f1xx.c ****        /* HSE oscillator clock selected as PREDIV1 clock entry */
 289:Src/system_stm32f1xx.c ****        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
 290:Src/system_stm32f1xx.c ****  #else
 291:Src/system_stm32f1xx.c ****         /* HSE selected as PLL clock entry */
 292:Src/system_stm32f1xx.c ****         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
 293:Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
 294:Src/system_stm32f1xx.c ****           SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
 295:Src/system_stm32f1xx.c ****         }
 296:Src/system_stm32f1xx.c ****         else
 297:Src/system_stm32f1xx.c ****         {
 298:Src/system_stm32f1xx.c ****           SystemCoreClock = HSE_VALUE * pllmull;
 299:Src/system_stm32f1xx.c ****         }
 300:Src/system_stm32f1xx.c ****  #endif
 301:Src/system_stm32f1xx.c ****       }
 302:Src/system_stm32f1xx.c **** #else
 303:Src/system_stm32f1xx.c ****       pllmull = pllmull >> 18U;
 304:Src/system_stm32f1xx.c ****       
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 8


 305:Src/system_stm32f1xx.c ****       if (pllmull != 0x0DU)
 306:Src/system_stm32f1xx.c ****       {
 307:Src/system_stm32f1xx.c ****          pllmull += 2U;
 308:Src/system_stm32f1xx.c ****       }
 309:Src/system_stm32f1xx.c ****       else
 310:Src/system_stm32f1xx.c ****       { /* PLL multiplication factor = PLL input clock * 6.5 */
 311:Src/system_stm32f1xx.c ****         pllmull = 13U / 2U; 
 312:Src/system_stm32f1xx.c ****       }
 313:Src/system_stm32f1xx.c ****             
 314:Src/system_stm32f1xx.c ****       if (pllsource == 0x00U)
 315:Src/system_stm32f1xx.c ****       {
 316:Src/system_stm32f1xx.c ****         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 317:Src/system_stm32f1xx.c ****         SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
 318:Src/system_stm32f1xx.c ****       }
 319:Src/system_stm32f1xx.c ****       else
 320:Src/system_stm32f1xx.c ****       {/* PREDIV1 selected as PLL clock entry */
 321:Src/system_stm32f1xx.c ****         
 322:Src/system_stm32f1xx.c ****         /* Get PREDIV1 clock source and division factor */
 323:Src/system_stm32f1xx.c ****         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
 324:Src/system_stm32f1xx.c ****         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
 325:Src/system_stm32f1xx.c ****         
 326:Src/system_stm32f1xx.c ****         if (prediv1source == 0U)
 327:Src/system_stm32f1xx.c ****         { 
 328:Src/system_stm32f1xx.c ****           /* HSE oscillator clock selected as PREDIV1 clock entry */
 329:Src/system_stm32f1xx.c ****           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
 330:Src/system_stm32f1xx.c ****         }
 331:Src/system_stm32f1xx.c ****         else
 332:Src/system_stm32f1xx.c ****         {/* PLL2 clock selected as PREDIV1 clock entry */
 333:Src/system_stm32f1xx.c ****           
 334:Src/system_stm32f1xx.c ****           /* Get PREDIV2 division factor and PLL2 multiplication factor */
 335:Src/system_stm32f1xx.c ****           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
 336:Src/system_stm32f1xx.c ****           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
 337:Src/system_stm32f1xx.c ****           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;  
 338:Src/system_stm32f1xx.c ****         }
 339:Src/system_stm32f1xx.c ****       }
 340:Src/system_stm32f1xx.c **** #endif /* STM32F105xC */ 
 341:Src/system_stm32f1xx.c ****       break;
 342:Src/system_stm32f1xx.c **** 
 343:Src/system_stm32f1xx.c ****     default:
 344:Src/system_stm32f1xx.c ****       SystemCoreClock = HSI_VALUE;
  99              		.loc 1 344 0
 100 0012 1C4B     		ldr	r3, .L15+4
 101              	.LVL2:
 102 0014 1C4A     		ldr	r2, .L15+8
 103 0016 1A60     		str	r2, [r3]
 345:Src/system_stm32f1xx.c ****       break;
 104              		.loc 1 345 0
 105 0018 02E0     		b	.L9
 106              	.LVL3:
 107              	.L13:
 265:Src/system_stm32f1xx.c ****       break;
 108              		.loc 1 265 0
 109 001a 1A4B     		ldr	r3, .L15+4
 110              	.LVL4:
 111 001c 1A4A     		ldr	r2, .L15+8
 112 001e 1A60     		str	r2, [r3]
 113              	.LVL5:
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 9


 114              	.L9:
 346:Src/system_stm32f1xx.c ****   }
 347:Src/system_stm32f1xx.c ****   
 348:Src/system_stm32f1xx.c ****   /* Compute HCLK clock frequency ----------------*/
 349:Src/system_stm32f1xx.c ****   /* Get HCLK prescaler */
 350:Src/system_stm32f1xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
 115              		.loc 1 350 0
 116 0020 174B     		ldr	r3, .L15
 117 0022 5B68     		ldr	r3, [r3, #4]
 118 0024 C3F30313 		ubfx	r3, r3, #4, #4
 119 0028 184A     		ldr	r2, .L15+12
 120 002a D15C     		ldrb	r1, [r2, r3]	@ zero_extendqisi2
 121              	.LVL6:
 351:Src/system_stm32f1xx.c ****   /* HCLK clock frequency */
 352:Src/system_stm32f1xx.c ****   SystemCoreClock >>= tmp;  
 122              		.loc 1 352 0
 123 002c 154A     		ldr	r2, .L15+4
 124 002e 1368     		ldr	r3, [r2]
 125 0030 CB40     		lsrs	r3, r3, r1
 126 0032 1360     		str	r3, [r2]
 353:Src/system_stm32f1xx.c **** }
 127              		.loc 1 353 0
 128 0034 7047     		bx	lr
 129              	.LVL7:
 130              	.L6:
 268:Src/system_stm32f1xx.c ****       break;
 131              		.loc 1 268 0
 132 0036 134B     		ldr	r3, .L15+4
 133              	.LVL8:
 134 0038 134A     		ldr	r2, .L15+8
 135 003a 1A60     		str	r2, [r3]
 269:Src/system_stm32f1xx.c ****     case 0x08U:  /* PLL used as system clock */
 136              		.loc 1 269 0
 137 003c F0E7     		b	.L9
 138              	.LVL9:
 139              	.L7:
 273:Src/system_stm32f1xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 140              		.loc 1 273 0
 141 003e 104A     		ldr	r2, .L15
 142 0040 5368     		ldr	r3, [r2, #4]
 143              	.LVL10:
 274:Src/system_stm32f1xx.c ****       
 144              		.loc 1 274 0
 145 0042 5268     		ldr	r2, [r2, #4]
 146              	.LVL11:
 277:Src/system_stm32f1xx.c ****       
 147              		.loc 1 277 0
 148 0044 C3F38343 		ubfx	r3, r3, #18, #4
 149              	.LVL12:
 150 0048 0233     		adds	r3, r3, #2
 151              	.LVL13:
 279:Src/system_stm32f1xx.c ****       {
 152              		.loc 1 279 0
 153 004a 12F4803F 		tst	r2, #65536
 154 004e 0AD0     		beq	.L14
 292:Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
 155              		.loc 1 292 0
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 10


 156 0050 0B4A     		ldr	r2, .L15
 157              	.LVL14:
 158 0052 5268     		ldr	r2, [r2, #4]
 159 0054 12F4003F 		tst	r2, #131072
 160 0058 0BD0     		beq	.L11
 294:Src/system_stm32f1xx.c ****         }
 161              		.loc 1 294 0
 162 005a 0D4A     		ldr	r2, .L15+16
 163 005c 02FB03F3 		mul	r3, r2, r3
 164              	.LVL15:
 165 0060 084A     		ldr	r2, .L15+4
 166 0062 1360     		str	r3, [r2]
 167 0064 DCE7     		b	.L9
 168              	.LVL16:
 169              	.L14:
 282:Src/system_stm32f1xx.c ****       }
 170              		.loc 1 282 0
 171 0066 0A4A     		ldr	r2, .L15+16
 172              	.LVL17:
 173 0068 02FB03F3 		mul	r3, r2, r3
 174              	.LVL18:
 175 006c 054A     		ldr	r2, .L15+4
 176 006e 1360     		str	r3, [r2]
 177 0070 D6E7     		b	.L9
 178              	.LVL19:
 179              	.L11:
 298:Src/system_stm32f1xx.c ****         }
 180              		.loc 1 298 0
 181 0072 054A     		ldr	r2, .L15+8
 182 0074 02FB03F3 		mul	r3, r2, r3
 183              	.LVL20:
 184 0078 024A     		ldr	r2, .L15+4
 185 007a 1360     		str	r3, [r2]
 186 007c D0E7     		b	.L9
 187              	.L16:
 188 007e 00BF     		.align	2
 189              	.L15:
 190 0080 00100240 		.word	1073876992
 191 0084 00000000 		.word	.LANCHOR0
 192 0088 00127A00 		.word	8000000
 193 008c 00000000 		.word	.LANCHOR1
 194 0090 00093D00 		.word	4000000
 195              		.cfi_endproc
 196              	.LFE66:
 198              		.global	APBPrescTable
 199              		.global	AHBPrescTable
 200              		.global	SystemCoreClock
 201              		.section	.data.SystemCoreClock,"aw",%progbits
 202              		.align	2
 203              		.set	.LANCHOR0,. + 0
 206              	SystemCoreClock:
 207 0000 0024F400 		.word	16000000
 208              		.section	.rodata.AHBPrescTable,"a",%progbits
 209              		.align	2
 210              		.set	.LANCHOR1,. + 0
 213              	AHBPrescTable:
 214 0000 00       		.byte	0
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 11


 215 0001 00       		.byte	0
 216 0002 00       		.byte	0
 217 0003 00       		.byte	0
 218 0004 00       		.byte	0
 219 0005 00       		.byte	0
 220 0006 00       		.byte	0
 221 0007 00       		.byte	0
 222 0008 01       		.byte	1
 223 0009 02       		.byte	2
 224 000a 03       		.byte	3
 225 000b 04       		.byte	4
 226 000c 06       		.byte	6
 227 000d 07       		.byte	7
 228 000e 08       		.byte	8
 229 000f 09       		.byte	9
 230              		.section	.rodata.APBPrescTable,"a",%progbits
 231              		.align	2
 234              	APBPrescTable:
 235 0000 00       		.byte	0
 236 0001 00       		.byte	0
 237 0002 00       		.byte	0
 238 0003 00       		.byte	0
 239 0004 01       		.byte	1
 240 0005 02       		.byte	2
 241 0006 03       		.byte	3
 242 0007 04       		.byte	4
 243              		.text
 244              	.Letext0:
 245              		.file 2 "c:\\program files (x86)\\gnu tools arm embedded\\7 2017-q4-major\\arm-none-eabi\\include\
 246              		.file 3 "c:\\program files (x86)\\gnu tools arm embedded\\7 2017-q4-major\\arm-none-eabi\\include\
 247              		.file 4 "Drivers/CMSIS/Include/core_cm3.h"
 248              		.file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
 249              		.file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
 250              		.file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
 251              		.file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS  X:\TMP\USER_T~1\ccLObCok.s 			page 12


DEFINED SYMBOLS
                            *ABS*:00000000 system_stm32f1xx.c
X:\TMP\USER_T~1\ccLObCok.s:16     .text.SystemInit:00000000 $t
X:\TMP\USER_T~1\ccLObCok.s:23     .text.SystemInit:00000000 SystemInit
X:\TMP\USER_T~1\ccLObCok.s:66     .text.SystemInit:00000040 $d
X:\TMP\USER_T~1\ccLObCok.s:73     .text.SystemCoreClockUpdate:00000000 $t
X:\TMP\USER_T~1\ccLObCok.s:80     .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
X:\TMP\USER_T~1\ccLObCok.s:190    .text.SystemCoreClockUpdate:00000080 $d
X:\TMP\USER_T~1\ccLObCok.s:234    .rodata.APBPrescTable:00000000 APBPrescTable
X:\TMP\USER_T~1\ccLObCok.s:213    .rodata.AHBPrescTable:00000000 AHBPrescTable
X:\TMP\USER_T~1\ccLObCok.s:206    .data.SystemCoreClock:00000000 SystemCoreClock
X:\TMP\USER_T~1\ccLObCok.s:202    .data.SystemCoreClock:00000000 $d
X:\TMP\USER_T~1\ccLObCok.s:209    .rodata.AHBPrescTable:00000000 $d
X:\TMP\USER_T~1\ccLObCok.s:231    .rodata.APBPrescTable:00000000 $d

NO UNDEFINED SYMBOLS
